Brain-inspired Cognition in Next-generation Racetrack Memories
نویسندگان
چکیده
Hyperdimensional computing (HDC) is an emerging computational framework inspired by the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike conventional frameworks operate numbers, HDC, like brain, uses high-dimensional random and capable one-shot learning. HDC based a well-defined set arithmetic operations highly error resilient. The core manipulate HD in bulk bit-wise fashion, offering many opportunities leverage parallelism. Unfortunately, von Neumann architectures, continuous movement among processor memory can make cognition task prohibitively slow energy intensive. Hardware accelerators only marginally improve related metrics. In contrast, even partial implementations inside provide considerable performance/energy gains as demonstrated prior work using memristors. This article presents architecture racetrack (RTM) conduct accelerate entire within memory. proposed solution requires minimal additional CMOS circuitry leveraging read operation across multiple domains RTMs called transverse (TR) realize exclusive-or ( XOR ) addition operations. To minimize overhead, RTM nanowire-based counting mechanism proposed. Using language recognition example workload, system reduces consumption 8.6× compared state-of-the-art in-memory implementation. Compared dedicated hardware design realized FPGA, RTM-based processing demonstrates 7.8× 5.3× improvements overall runtime consumption, respectively.
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ژورنال
عنوان ژورنال: ACM Transactions in Embedded Computing Systems
سال: 2022
ISSN: ['1539-9087', '1558-3465']
DOI: https://doi.org/10.1145/3524071